Construction Of Automatic Phase Changer

DESIGN CALCULATION
From fig 2: R1 and R2 from a potential divider to reduce the unregulated voltage to a low voltage of less than 5v at 160v ac input let vr2=1.5v

Where VR2 is the drop across R2 and v+ is the unregulated voltage from table 1 it can be seen that v+ 11v at 160av input
Let R1 =100k-2
R2=15.7k2
      =15k-2 preferred value
R3 and R4 from another potential divider for the reference letting a maximum adjustable reference of 3.5v and setting R3=1.5K-2

=5kv present (preferred value)
    R3=1.5kv and R4 = 5kv preset
For the comparator
Vour=Ao vin _ _ _ _ _ _ _ _ _ _ _ _ (3)
Where Ao open 100p voltage gain (usually 20,000 or more) (horowit2 and Winfield 2002)
And vin v+ - v -   - - - - - - - - - - - - - - - (4)
Vout will drop to v+ for the slightest positive different in voltage since Ao is of often very large (in order of 20,000).
As the public supply input drops below 1.5v reference, the out put of the comparator goes high to switch public supply to the output
ASCILLATOR CIRCUIT
The flip is a synchronous device and requires clock pulse to operate in its set and reset modes the unstable oscillator stage of 1kh2 using a 555 timer oscillator stage.
The timing and frequency of unstable oscillator is given by fizzler (1991) and Owen 1995.
T1=1.1c (R1+R2) secs - - - - - - - -- - - (5)
T2=0.693CR, secs - - - - - - - - - - - - - (6)
Where t1= on time and t2 =off time
F =   1.44    - - - - - - - -- - - - - -- - - - -- (7)
d (R1+2R2) c
Letting r1=5.1k -2 and c= 47nf for f = 1k h2
R2 =12.7k -2
    =12k – 2 preferred value
Hence, R5=5.1k -2 R6 = 12k 2 an c3 =47.f
FIG.3.UNSTABLE OSCILLATOR STAGE
FLIP FLOP SWITCHING TRANSISTOR STAGE
The flip act as a logic control while the transistor act as a switching circuit fig4 shows the circuit diagram of the flip flop and switching transistor